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參數(shù)資料
| 型號： | TPPM0115DR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.5 A SWITCHING CONTROLLER, 200 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 239K |
| 代理商： | TPPM0115DR |
TPPM0115
SWITCH MODE SYNCHRONOUS BUCK CONTROLLER
SLVS371A MARCH 2001 REVISED JUNE 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dc electrical characteristics, TA = 0°C to 55°C, VCC = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT
Output voltage
VCC = 11.4 V to 12.6 V, IL = 5 A to 10 A,
See Figure 8 for external components,
R1 = 0, R2 is not present
1
V
η
Efficiency
IL = 10 A,
See Figure 8
86%
IQ
Quiescent current
V(SEN) = < 1 V or >1.3 V,
VOUT = 1 V to 1.3 V
2
mA
VO(IO)
Load regulation
VO(VI)
Line regulation
See Figure 8
1%
Temperature regulation
See Figure 8
1%
VOH(DRVH)
Upper drive output voltage
V(SEN) = 0.9 V,
IOH = 200 mA
VCC3V
V
VOL(DRVH)
Upper drive output voltage
V(SEN) = 1.2 V,
IOL = 200 mA
1
V
VOH(DRVL)
Lower drive output voltage
V(SEN) = 1.2 V,
V(PHASE) < 0 V
IOH = 200 mA
5
V
VOL(DRVL)
Lower drive output voltage
V(SEN) = 0.9 V,
IOL = 200 mA
1
V
IIH
Phase input current
V(SEN) = 0.9 V,
V(PHASE) = 5 V
100
A
IIL
Phase input current
V(SEN) = 1.2 V,
V(PHASE) = 0.3 V
50
A
V(PWRGD)
Sense output voltage for
Ramp up sense input until PWRGD
transition to high
VOUT*
0.86
VOUT*
0.96
V
V(PWRGD)
Sense output voltage for
PWRGD detection range
Ramp down sense input until PWRGD
transition to low
VOUT*
0.63
VOUT*
0.71
V
IBIAS
Sense feedback bias current
V(SEN) = 1.08 V
5
A
ac electrical characteristics, TA = 0°C to 55°C, VCC = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fsw
Switching frequency
Measured at DRVH terminal
200
kHz
tr
Output rise time for both DRVH and DRVL
V(DRVH) → 0 V to 8 V,
V(SEN) → 1.1 V to 0.9 V
50
ns
tr
Output rise time for both DRVH and DRVL
V(DRVL) → 0 V to 8 V,
V(SEN) → 0.9 V to 1.1 V
50
ns
tf
Output fall time for both DRVH and DRVL
V(DRVH) → 8 V to 0 V,
V(SEN) → 0.9 V to 1.1 V
50
ns
tf
Output fall time for both DRVH and DRVL
V(DRVL) → 8 V to 0 V,
V(SEN) → 1.1 V to 0.9 V
50
ns
td
Power good signal delay
Delay time for V(SEN) >V(PWRGD) to PWRGD
transitioning high
1
5
ms
tdt
Dead time between DRVH and DRVL
V(SEN) → 1.1 V to 0.9 V,
Delay between V(DRVL) at 0 V and V(DRVH) = 1.5 V
50
ns
tdt
Dead time between DRVH and DRVL
switch conduction
V(SEN) → 0.9 V to 1.1 V,
Delay between V(DRVH) at 0 V and V(DRVL) = 1.5 V
50
ns
thermal characteristics
MIN
TYP
MAX
UNIT
RθJC
Thermal impedance, junction-to-case
50
°C/W
RθJA
Thermal impedance, junction-to-ambient
178
°C/W
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