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參數資料
| 型號： | TPIC6E175NE |
| 英文描述： | 1-Bit D-Type Latch |
| 中文描述： | 1位D型鎖存器 |
| 文件頁數： | 6/9頁 |
| 文件大小： | 142K |
| 代理商： | TPIC6E175NE |
TPIC6595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS010A
–
APRIL 1992
–
REVISED OCTOBER 1995
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.25 A
IF
0
IRM
25% of IRM
ta
trr
di/dt = 20 A/
μ
s
+
–
2500
μ
F
250 V
L = 1 mH
IF
(see Note B)
RG
VGG
(see Note A)
Driver
TP A
50
Circuit
Under
Test
DRAIN
25 V
t1
t3
t2
TP K
TEST CIRCUIT
CURRENT WAVEFORM
NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/
μ
s. A VGG double-pulse train is used to set IF = 0.25 A,
where t1 = 10
μ
s, t2 = 7
μ
s, and t3 = 3
μ
s.
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
15 V
0.11
100 mH
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
tw
tav
IAS = 1 A
V(BR)DSX = 45 V
MIN
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
VCC
DRAIN
LGND
SRCLR
SER IN
G
SRCK
RCK
Word
Generator
(see Note A)
DUT
PGND
5 V
VDS
ID
2
8
13
3
12
9
19
1, 10, 11, 20
4
–
7,
14
–
17
5 V
0 V
NOTES: A. The word generator has the following characteristics: tr
≤
10 ns, tf
≤
10 ns, ZO = 50
.
B. Input pulse duration, tw, is increased until peak current IAS = 1 A.
Energy test level is defined as EAS = IAS
×
V(BR)DSX
×
tav/2 = 75 mJ, where tav = avalanche time.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
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