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| 型號： | TP80C51FA1 |
| 英文描述： | (193.00 k) |
| 中文描述： | （193.00十一） |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 193K |
| 代理商： | TP80C51FA1 |
AUTOMOTIVE 80C51FA/83C51FA
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char-
acter is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
T
AVLL
e
Time from Address Valid to ALE Low
T
LLPL
e
Time from ALE Low to PSEN Low
AC CHARACTERISTICS
(T
A
e b
40
§
C to
a
125
§
C, V
CC
e
5V
g
10%, V
SS
e
0V, Load Capacitance
for Port 0, ALE/PROG and PSEN
e
100 pF, Load Capacitance for All Other Outputs
e
80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
Units
Min
Max
Min
Max
1/T
CLCL
Oscillator Frequency
3.5
16
MHz
T
LHLL
ALE Pulse Width
127
2T
CLCL
b
40
T
CLCL
b
40
T
CLCL
b
30
ns
T
AVLL
Address Valid to ALE Low
43
ns
T
LLAX
Address Hold After ALE Low
53
ns
T
LLIV
ALE Low to Valid Instruction In
224
4T
CLCL
b
110
ns
T
LLPL
ALE Low to PSEN Low
53
T
CLCL
b
30
3T
CLCL
b
45
ns
T
PLPH
PSEN Pulse Width
205
ns
T
PLIV
PSEN Low to Valid Instruction In
135
3T
CLCL
b
115
ns
T
PXIX
Input Instr Hold After PSEN Trans
0
0
ns
T
PXIZ
Input Instr Float After PSEN Trans
59
T
CLCL
b
25
5T
CLCL
b
115
ns
T
AVIV
Address to Valid Instruction In
302
ns
T
PLAZ
PSEN Low to Address Float
10
10
ns
T
RLRH
RD Pulse Width
400
6T
CLCL
b
100
6T
CLCL
b
100
ns
T
WLWH
WR Pulse Width
400
ns
T
RLDV
RD Low to Valid Data In
242
5T
CLCL
b
175
ns
T
RHDX
Data Hold After RD High
b
10
b
10
ns
T
RHDZ
Data Float After RD High
107
2T
CLCL
b
60
8T
CLCL
b
160
9T
CLCL
b
175
3T
CLCL
a
50
ns
T
LLDV
ALE Low to Valid Data In
507
ns
T
AVDV
Address Valid to Valid Data In
575
ns
T
LLWL
ALE Low to RD or WR Low
200
300
3T
CLCL
b
50
4T
CLCL
b
130
T
CLCL
b
50
T
CLCL
b
50
7T
CLCL
b
150
ns
T
AVWL
Data Valid to WR Low
203
ns
T
QVWX
Address Valid before WR Low
23
ns
T
WHQX
Data Hold after WR High
33
ns
T
QVWH
Data Valid to WE High
433
ns
T
RLAZ
RD Low to Address Float
0
0
ns
T
WHLH
RD or WR High to ALE High
43
123
T
CLCL
b
40
T
CLCL
a
40
ns
10
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