參數(shù)資料
型號: TP5335K1
廠商: SUPERTEX INC
元件分類: 功率晶體管
英文描述: P-Channel Enhancement-Mode Vertical DMOS FETs
中文描述: 85 mA, 350 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-236AB
封裝: TO-236AB, 3 PIN
文件頁數(shù): 1/2頁
文件大?。?/td> 434K
代理商: TP5335K1
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
TP5335
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
Note: See Package Outline section for dimensions.
Package Options
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C
ISS
and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode
High input impedance and high gain
Complementary N- and P-channel devices
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Analog switches
Power Management
Telecom switches
TO-236AB
(SOT-23)
top view
Gate
Source
Drain
P-Channel Enhancement-Mode
Vertical DMOS FETs
Low Threshold
Absolute Maximum Ratings
Drain-to-Source Voltage
BV
DSS
BV
DGS
±
20V
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
-55
°
C to +150
°
C
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
300
°
C
Product Objective Specification
BV
DSS
/
BV
DGS
R
DS(ON)
(max)
V
GS(th)
(max)
TO-236AB*
Wafer
-350V
30
-2.4V
TP5335K1
TP5335NW
*Same as SOT-23. All units shipped on 3,000 piece carrier tape reels.
Ordering Information
Order Number/Package
Product marking for SOT-23
Where *=2-week alpha date code
P3S
相關(guān)PDF資料
PDF描述
TP5335NW P-Channel Enhancement-Mode Vertical DMOS FETs
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