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參數(shù)資料
| 型號： | TP13057BN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CAPACITOR 18000UF 35V ELECT TSUP |
| 中文描述： | 整體式串行接口的PCM編解碼器和過濾器 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 249K |
| 代理商： | TP13057BN |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS042A – MAY 1990 – REVISED JULY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
VCC
DGND
VBB
Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3054B, TP3057B, TP13054B, and TP13057B devices when power
is first applied, placing it into the power-down mode. DX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
Table 1. Selection of Master-Clock Frequencies
BCLKR/CLKSEL
MASTER-CLOCK FREQUENCY SELECTED
TP13054B, TP3054B
TP13057B, TP3057B
Clock Input
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input L
(sync mode only)
2.048 MHz
1.536 MHz or 1.544 MHz
Logic Input H (open)
(sync mode only)
1.536 MHz or 1.544 MHz
2.048 MHz
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
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| TP3054B | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3054BDW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3054BN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3057B | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3057BDW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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