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參數(shù)資料
| 型號： | TOOLSTICK342DC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 265/276頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD TOOLSTCK C8051F342 |
| 標準包裝： | 1 |
| 系列： | ToolStick |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | C8051F342 |
| 所含物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 626 (CN2011-ZH PDF) |
| 配用： | 336-1345-ND - TOOLSTICK BASE ADAPTER |
| 相關(guān)產(chǎn)品： | 336-1345-5-ND - IC 8051 MCU 64K FLASH MEM 32-QFN 336-1300-ND - IC 8051 MCU FLASH 64K 32LQFP |
| 其它名稱： | 336-1482 |
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Rev. 1.3
89
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 9.13). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “15.1. Priority Crossbar
Decoder” on page 144 for complete details on configuring the Crossbar). In the typical configuration, the
external interrupt pin should be skipped in the crossbar and configured as open-drain with the pin latch set
to '1'.
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 9.4.
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write/erase operations and USB FIFO MOVX accesses (see
Section “13.2. Accessing USB FIFO Space” on page 115). Interrupt service latency will be increased for
interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the
standard interrupt service procedure (as described above) and the amount of time the CPU is stalled.
IT0
IN0PL
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
10
Active low, edge sensitive
10
Active low, edge sensitive
11
Active high, edge sensitive
11
Active high, edge sensitive
00
Active low, level sensitive
00
Active low, level sensitive
01
Active high, level sensitive
01
Active high, level sensitive
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