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8XC196MD
PROCES
S
INFORMATION
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability infor-
mation is available in the
Intel
Quality System
Handbook
.
272323–2
NOTE:
EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 2. The 8XC196MD Family Nomenclature
Table 1. Thermal Characteristics
Package
Type
θ
ja
θ
jc
PLCC
35
°
C/W
56
°
C/W
13
°
C/W
12
°
C/W
QFP
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
Table 2. 8XC196MD Memory Map
Description
Address
External Memory or I/O
0FFFFH
06000H
Internal ROM/EPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201CH
Reserved. Must Contain 20H
(Note 5)
201BH
CCB1
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
CCB0
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
SFR’s
1FFFH
1F00H
External Memory
1EFFH
0200H
488 Bytes Register RAM (Note 1)
01FFH
0018H
CPU SFR’s (Notes 1. 3)
0017H
0000H
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196MC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
x