參數(shù)資料
型號(hào): TMX320LF2402APGS
英文描述: DSP|16-BIT|CMOS|QFP|64PIN|PLASTIC
中文描述: 數(shù)字信號(hào)處理器| 16位|的CMOS | QFP封裝| 64管腳|塑料
文件頁數(shù): 105/132頁
文件大?。?/td> 1707K
代理商: TMX320LF2402APGS
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
105
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
external memory interface
ready-on-read
timings
switching characteristics over recommended operating conditions for an external memory
interface ready-on-read (see Figure 46)
PARAMETER
MIN
MAX
UNIT
td(COL-A)RD
Delay time, CLKOUT low to address valid
8
ns
timing requirements for an external memory interface ready-on-read (see Figure 46)
MIN
MAX
UNIT
th(RDY)COH
Hold time, READY after CLKOUT high
3
ns
tsu(D)RD
tv(RDY)ARD
tsu(RDY)COH
Setup time, read data before RD strobe inactive high
8
ns
Valid time, READY after address valid on read
2
ns
Setup time, READY before CLKOUT high
22
ns
th(RDY)COH
CLKOUT
PS, DS, IS
RD
D[0:15]
STRB
A[0:15]
td(COL
A)RD
tv(RDY)ARD
tsu(RDY)COH
READY
Wait Cycle
tsu(D)RD
The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more details.
Figure 46. Ready-on-Read Timings
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