參數(shù)資料
型號： TMX320F28069PZA
廠商： Texas Instruments
文件頁數(shù)： 90/174頁
文件大小： 0K
描述： IC MCU 32BIT 128KB FLASH 100LQFP
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Piccolo F2806x
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 256KB（128K x 16）
程序存儲器類型： 閃存
RAM 容量： 50K x 16
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Table 2-5. Terminal Functions(1) (continued)
PIN NO.
PIN NAME
I/O/Z
DESCRIPTION
PZ
PN
PZP
PFP
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is
controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
XCLKOUT
See GPIO18
O/Z
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3.
The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate
to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection.
This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if
available, must be tied to GND and the on-chip crystal oscillator must be disabled via
bit 14 in the CLKCTL register. If a crystal or resonator is used, the XCLKIN path must
See GPIO19 and
XCLKIN
I
be disabled by bit 13 in the CLKCTL register.
GPIO38
NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for
normal device operation may need to incorporate some hooks to disable this path
during debug using the JTAG connector. This is to prevent contention with the TCK
signal, which is active during JTAG debug sessions. The zero-pin internal oscillators
may be used during this time to clock the device.
On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic
resonator must be connected across X1 and X2. In this case, the XCLKIN path must
X1
60
48
I
be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to
GND.
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
X2
59
47
O
connected across X1 and X2. If X2 is not used, it must be left unconnected.
RESET
Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-
reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is
needed to generate a reset pulse. During a power-on or brown-out condition, this pin is
driven low by the device. See Section 4.3, Electrical Characteristics, for thresholds of
the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset
occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin
XRS
11
9
I/O
to assert a device reset. In this case, it is recommended that this pin be driven by an
open-drain device. An R-C circuit must be connected to this pin for noise immunity
reasons. Regardless of the source, a device reset causes the device to terminate
execution. The program counter points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution begins at the location designated by
the program counter. The output buffer of this pin is an open-drain with an internal
pullup.
ADC, COMPARATOR, ANALOG I/O
ADCINA7
16
–
I
ADC Group A, Channel 7 input
ADCINA6
17
14
I
ADC Group A, Channel 6 input
COMP3A
I
Comparator Input 3A
AIO6
I/O
Digital AIO 6
ADCINA5
18
15
I
ADC Group A, Channel 5 input
ADCINA4
19
16
I
ADC Group A, Channel 4 input
COMP2A
I
Comparator Input 2A
AIO4
I/O
Digital AIO 4
ADCINA3
20
–
I
ADC Group A, Channel 3 input
ADCINA2
21
17
I
ADC Group A, Channel 2 input
COMP1A
I
Comparator Input 1A
AIO2
I/O
Digital AIO 2
ADCINA1
22
18
I
ADC Group A, Channel 1 input
ADC Group A, Channel 0 input.
ADCINA0
23
19
I
NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices
and their use is mutually exclusive to one another.
22
Device Overview
Copyright 2010–2012, Texas Instruments Incorporated
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