參數資料
型號： TMX320DM648ZUT900
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數字媒體處理器
文件頁數： 155/166頁
文件大?。?/td> 1341K
代理商： TMX320DM648ZUT900
www.ti.com
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6.20 Timers
6.20.1 General-Purpose Timers
6.20.2 Timer Peripheral Register Description(s)
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The DM647/DM648 devices have four 64-bit general-purpose timers of which only Timer 0 and Timer 1
have external input/output. The timers can be used to: time events, count events, generate pulses,
interrupt the CPU, and send synchronization events to the EDMA3 channel controller.
The DM647/DM648 devices have four general-purpose timers, Timer 0, Timer 1, Timer 2, and Timer 3
each of which can be configured as a general-purpose timer or a watchdog timer. When configured as a
general-purpose timer, each timer can be programmed as a 64-bit timer or as two separate 32-bit timers.
Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx
and TOUTLx are connected to the low counter. The high counter does not have any external device pins.
For more detailed information, see the
TMS320DM647DM648 DSP 64-Bit Timer User's Guide
(literature
number
SPRUEL0
).
Table 6-71. Timer 0 Registers
HEX ADDRESS RANGE
0x0204 4400
0x0204 4404
0x0204 4410
0x0204 4414
0x0204 4418
0x0204 441C
0x0204 4420
0x0204 4424
0x0x0204 4428 - 0x0204 44FF
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
-
DESCRIPTION
Reserved
Timer 0 Emulation Management/Clock Speed Register
Timer 0 Counter Register 12
Timer 0 Counter Register 34
Timer 0 Period Register 12
Timer 0 Period Register 34
Timer 0 Control Register
Timer 0 Global Control Register
Reserved
Table 6-72. Timer 1 Registers
HEX ADDRESS RANGE
0x0204 4800
0x0204 4804
0x0204 4810
0x0204 4814
0x0204 4818
0x0204 481C
0x0204 4820
0x0204 4824
0x0204 4828 - 0x0204 48FF
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
-
DESCRIPTION
Reserved
Timer 1 Emulation Management/Clock Speed Register
Timer 1 Counter Register 12
Timer 1 Counter Register 34
Timer 1 Period Register 12
Timer 1 Period Register 34
Timer 1 Control Register
Timer 1 Global Control Register
Reserved
Table 6-73. Timer 2 Registers
HEX ADDRESS RANGE
0x0204 4C00
0x0204 4C04
0x0204 4C10
0x0204 4C14
0x0204 4C18
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
DESCRIPTION
Reserved
Timer 2 Emulation Management/Clock Speed Register
Timer 2 Counter Register 12
Timer 2 Counter Register 34
Timer 2 Period Register 12
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Peripheral Information and Electrical Specifications
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