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P
1
Digital Media System-on-Chip (DMSoC)
1.1
Features
High-Performance Digital Media SoC
–
594-MHz C64x+ Clock Rate
–
297-MHz ARM926EJ-S Clock Rate
–
Eight 32-Bit C64x+ Instructions/Cycle
–
4752 C64x+ MIPS
–
Fully Software-Compatible With C64x /
ARM9
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+ DSP Core
–
Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
–
Load-Store Architecture With Non-Aligned
Support
–
64 32-Bit General-Purpose Registers
–
Instruction Packing Reduces Code Size
–
All Instructions Conditional
–
Additional C64x+ Enhancements
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Operation
C64x+ Instruction Set Features
–
Byte-Addressable (8-/16-/32-/64-Bit Data)
–
8-Bit Overflow Protection
–
Bit-Field Extract, Set, Clear
–
Normalization, Saturation, Bit-Counting
–
Compact 16-Bit Instructions
–
Additional Instructions to Support Complex
Multiplies
C64x+ L1/L2 Memory Architecture
–
32K-Byte L1P Program RAM/Cache (Direct
Mapped)
–
80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
–
64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
ARM926EJ-S (MPU) Core
–
Support for 32-Bit and 16-Bit (Thumb
Mode) Instruction Sets
–
DSP Instruction Extensions and Single
Cycle MAC
–
ARM Jazelle Technology
–
EmbeddedICE-RT Logic for Real-Time
Debug
ARM9 Memory Architecture
–
16K-Byte Instruction Cache
–
8K-Byte Data Cache
–
16K-Byte RAM
–
16K-Byte ROM
Embedded Trace Buffer (ETB11) With 4KB
Memory for ARM9 Debug
Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
–
Front End Provides:
CCD and CMOS Imager Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Histogram Module
Auto-Exposure, Auto-White Balance and
Auto-Focus Module
Resize Engine
Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
–
Back End Provides:
Hardware On-Screen Display (OSD)
Four 54-MHz DACs for a Combination of
Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
Component (YPbPr or RGB) Video
(Progressive)
Digital Output
8-/16-bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C6000, I
2
C bus, I
2
C-bus are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCT
formative or PREVIEW
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
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concerns
products
in
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Copyright 2005, Texas Instruments Incorporated