參數(shù)資料
型號(hào): TMX320C6415TGLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 128/140頁
文件大?。?/td> 2033K
代理商: TMX320C6415TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
128
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY]
timing requirements for UXCLK
(see Figure 57)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tc(UXCK)
tw(UXCKH)
tw(UXCKL)
tt(UXCK)
Cycle time, UXCLK
20
ns
2
Pulse duration, UXCLK high
0.4tc(UXCK)
0.4tc(UXCK)
0.6tc(UXCK)
0.6tc(UXCK)
ns
3
Pulse duration, UXCLK low
ns
4
Transition time, UXCLK
2
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
UXCLK
1
2
3
4
4
Figure 57. UXCLK Timing
timing requirements for URCLK
(see Figure 58)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tc(URCK)
tw(URCKH)
tw(URCKL)
tt(URCK)
Cycle time, URCLK
20
ns
2
Pulse duration, URCLK high
0.4tc(URCK)
0.4tc(URCK)
0.6tc(URCK)
0.6tc(URCK)
ns
3
Pulse duration, URCLK low
ns
4
Transition time, URCLK
2
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
URCLK
1
2
3
4
4
Figure 58. URCLK Timing
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