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      參數(shù)資料
      型號: TMX320C6204GGP167
      廠商: Texas Instruments, Inc.
      英文描述: E Core
      中文描述: 定點數(shù)字信號處理器
      文件頁數(shù): 58/83頁
      文件大?。?/td> 1176K
      代理商: TMX320C6204GGP167
      TMS320C6211, TMS320C6211B
      FIXED-POINT DIGITAL SIGNAL PROCESSORS
      SPRS073K
      AUGUST 1998
      REVISED MARCH 2004
      58
      POST OFFICE BOX 1443
      HOUSTON, TEXAS 77251
      1443
      HOLD/HOLDA TIMING
      timing requirements for the HOLD/HOLDA cycles
      (see Figure 29)
      NO.
      150
      167
      UNIT
      MIN
      MAX
      3
      t
      oh(HOLDAL-HOLDL)
      Output hold time, HOLD low after HOLDA low
      E
      ns
      E = ECLKIN period in ns
      switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
      (see Figure 29)
      NO.
      PARAMETER
      150
      167
      UNIT
      MIN
      2E
      MAX
      1
      2
      4
      5
      t
      d(HOLDL-EMHZ)
      t
      d(EMHZ-HOLDAL)
      t
      d(HOLDH-EMLZ)
      t
      d(EMLZ-HOLDAH)
      Delay time, HOLD low to EMIF Bus high impedance
      Delay time, EMIF Bus high impedance to HOLDA low
      Delay time, HOLD high to EMIF Bus low impedance
      Delay time, EMIF Bus low impedance to HOLDA high
      §
      ns
      ns
      ns
      ns
      0
      2E
      7E
      2E
      2E
      0
      E = ECLKIN period in ns
      EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
      §
      All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
      time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
      HOLD
      HOLDA
      EMIF Bus
      DSP Owns Bus
      External Requestor
      Owns Bus
      DSP Owns Bus
      C6211/C6211B
      C6211/C6211B
      1
      3
      2
      5
      4
      EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
      Figure 29. HOLD/HOLDA Timing
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