
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K 
 AUGUST 1998 
 REVISED MARCH 2004
54
POST OFFICE BOX 1443 
 HOUSTON, TEXAS 77251
1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
EA12
EA[21:13]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 23. SDRAM Write Command