參數(shù)資料
型號: TMSC6701
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FLOATING POINT DIGITAL SIGNAL PROCESSOR
中文描述: 浮點(diǎn)數(shù)字信號處理器
文件頁數(shù): 1/64頁
文件大?。?/td> 862K
代理商: TMSC6701
.
SPRS067E – MAY 1998 – REVISED MAY 2000
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Highest Performance Floating-Point Digital
Signal Processor (DSP) TMS320C6701
– 8.3-, 6.7-, 6-ns Instruction Cycle Time
– 120-, 150-, 167-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1 GFLOPS
– TMS320C6201 Fixed-Point DSP
Pin-Compatible
VelociTI
Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional
Units:
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions
– Hardware Support for IEEE
Double-Precision Instructions
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
– 52M-Byte Addressable External Memory
Space
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola
)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
)
Boundary-Scan-Compatible
352-Pin Ball Grid Array (BGA) Package
(GJC Suffix)
0.18-
μ
m/5-Level Metal Process
– CMOS Technology
3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
3.3-V I/Os, 1.9-V Internal (167-MHz Only)
Copyright
2000, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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26
GJC (352-PIN BGA) PACKAGE
(BOTTOM VIEW)
VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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