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參數(shù)資料
| 型號： | TMS370C736AFNT |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 711K |
| 代理商： | TMS370C736AFNT |
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TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
program ROM
The program ROM consists of 16K bytes of mask programmable read-only memory. The program ROM is used
for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device
fabrication. Refer to Figure 3 for ROM memory map.
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx36 CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
generated internally, while one (RESET pin) is controlled externally. These actions are as follows:
PACT watchdog (WD) timer.
A watchdog-generated reset occurs if an improper value is written to the WD
key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370
User’s Guide(literature number SPNU127) for more information.
Oscillator reset.
Reset occurs when the oscillator operates outside of the recommended operating range.
See the TMS370 User’s Guide(literature number SPNU127) for more information.
External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 User’s Guide(literature number SPNU127) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x36 device to reset external system components. Additionally, if a cold start (V
CC
is off
for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4) and the cold-start flag
(COLD START, SCCR0.7) to determine the source of the reset. A reset does not clear these flags.Table 6 lists
the reset sources. If none of the sources indicated in Table 6 caused the reset, then the RESET pin was pulled
low by the external hardware or the PACT module’s watchdog.
Table 6. Reset Sources
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SCCR0
1010h
P010
4
OSC FLT FLAG
Oscillator out of range
1.
The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
2.
Registers A and B are initialized to 00h (no other RAM is changed).
3.
The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4.
The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5.
Program execution begins with an opcode fetch from the address pointed to the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.
Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments, and addresses 7FECh through 7FFFh are reserved for
interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and
7FDFh.
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