
TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SPI slave mode external timing characteristics and requirements (see Note 11 and Figure 21)
NO.
MIN
MAX
UNIT
45
tc(SPC)S
tw(SPCL)S
tw(SPCH)S
td(SPCL-SOMIV)S
tv(SPCH-SOMI)S
tsu(SIMO-SPCH)S
tv(SPCH-SIMO)S
Cycle time, SPICLK
8tc
4tc– 45
4tc– 45
ns
46
Pulse duration, SPICLK low
0.5tc(SPC)S+45
0.5tc(SPC)S+45
3.25tc + 130
ns
47
Pulse duration, SPICLK high
ns
48
Delay time, SPISOMI valid after SPICLK low (polarity = 1)
ns
49
Valid time, SPISOMI data valid after SPICLK high (polarity =1)
tw(SPCH)S
0
ns
50
Setup time, SPISIMO to SPICLK high (polarity = 1)
ns
51
Valid time, SPISIMO data after SPICLK high (polarity = 1)
3tC + 100
ns
NOTE 11: tc = system clock cycle time = 1/SYSCLK
Data Valid
Data Valid
SPISOMI
SPISIMO
SPICLK
51
50
49
48
45
47
46
The diagram is for polarity = 1. SPICLK is inverted when polarity = 0.
Figure 21. SPI Slave External Timing