參數(shù)資料
型號： TMS320VC546PZ2-50
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 39/132頁
文件大小： 1707K
代理商： TMS320VC546PZ2-50
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
240xA legend for the internal hardware (continued)
Table 4. Legend for the 240xA DSP CPU Internal Hardware (Continued)
SYMBOL
NAME
DESCRIPTION
PREG
Product Register
32-bit register holds results of 16
×
16 multiply
0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle
overhead.
PSCALE
Product-Scaling
Shifter
STACK
Stack
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep.
TREG
Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1
—
except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 9 shows the organization of status registers ST0 and ST1, indicating all status bits contained
in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status register
field definitions.
15
13
12
11
10
9
8
0
ST0
ARP
OV
OVM
1
INTM
DP
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST1
ARB
CNF
TC
SXM
C
1
1
1
1
XF
1
1
PM
Figure 9. Organization of Status Registers ST0 and ST1
Table 5. Status Register Field Definitions
FIELD
FUNCTION
ARB
Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.
ARP
Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.
C
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.
CNF
On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.
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