
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
105
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
external memory interface
ready-on-read
timings
switching characteristics over recommended operating conditions for an external memory
interface ready-on-read (see Figure 46)
PARAMETER
MIN
MAX
UNIT
td(COL-A)RD
Delay time, CLKOUT low to address valid
8
ns
timing requirements for an external memory interface ready-on-read (see Figure 46)
MIN
MAX
UNIT
th(RDY)COH
Hold time, READY after CLKOUT high
–
3
ns
tsu(D)RD
tv(RDY)ARD
tsu(RDY)COH
Setup time, read data before RD strobe inactive high
8
ns
Valid time, READY after address valid on read
–
2
ns
Setup time, READY before CLKOUT high
22
ns
th(RDY)COH
CLKOUT
PS, DS, IS
RD
D[0:15]
STRB
A[0:15]
td(COL
–
A)RD
tv(RDY)ARD
tsu(RDY)COH
READY
Wait Cycle
tsu(D)RD
The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more details.
Figure 46. Ready-on-Read Timings