參數(shù)資料
型號： TMS320VC5409ZGU100
廠商： Texas Instruments
文件頁數(shù)： 10/93頁
文件大?。?/td> 0K
描述： IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝： 160
系列： TMS320C54x
類型： 定點
接口： 主機(jī)接口，McBSP
時鐘速率： 100MHz
非易失內(nèi)存： ROM（32 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-BGA MICROSTAR（12x12）
包裝： 托盤
配用： 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Introduction
18
April 1999 Revised October 2008
SPRS082F
Table 22. Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O
INTERNAL
TERMINAL
NAME
DESCRIPTION
I/O
PIN STATE
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS (CONTINUED)
BDX0
BDX1
BDX2
O/Z
Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins
can be used as general-purpose I/O by setting XIOEN = 1.
These pins are placed into the high-impedance state when OFF is low.
BFSX0
BFSX1
BFSX2
I/O/Z
Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the
transmit-data process over BDX pin. If RS is asserted when BFSX is configured as output, then
BFSX is turned into input mode by the reset operation. When not being used as data-transmit
synchronization pins, these pins can be used as general-purpose I/O by setting XIOEN = 1.
These pins are placed into the high-impedance state when OFF is low.
HOST-PORT INTERFACE SIGNALS
SECONDARY
PRIMARY
HA15 HA0
Bus holders
available
I/O/Z
A15 A0
O/Z
These pins can be used to address internal memory via the HPI
when the HPI16 pin is high. The sixteen address pins, A15 to A0,
are multiplexed to transfer address between the core CPU and
external data/program memory, I/O devices, or HPI in 16-bit mode.
The address bus includes bus holders to reduce the static power
dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external bias resistors on unused pins. When
the address bus is not being driven by the 5409, the bus holders
keep the pins at the logic level that was most recently driven. The
address bus holders of the 5409 are disabled at reset, and can be
enabled/disabled via the HBH bit of the BSCR.
HD15 HD0
Bus holders
available
I/O/Z
D15 D0
O/Z
These pins can be used to read/write internal memory via the HPI
when the HPI16 pin is high. The sixteen data pins, D15 to D0, are
multiplexed to transfer data between the core CPU and external
data/program memory, I/O devices, or HPI in 16-bit mode. The data
bus is placed in the high-impedance state when not outputting or
when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
The data bus includes bus holders to reduce the static power
dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external bias resistors on unused pins. When
the data bus is not being driven by the 5409, the bus holders keep
the pins at the logic level that was most recently driven. The data
bus holders of the 5409 are disabled at reset, and can be
enabled/disabled via the BH bit of the BSCR.
HD7 – HD0
Bus holders
available
I/O/Z
Parallel bidirectional data bus. When the HPI is disabled or when the HPI16 pin is high, these pins
can also be used as general-purpose I/O pins. HD7–HD0 are placed in the high-impedance state
when not outputting data or when OFF is low.
The HPI data bus includes bus holders to reduce the static power dissipation caused by floating,
unused pins. When the HPI data bus is not being driven by the 5409, the bus holders keep the pins
at the logic level that was most recently driven. The HPI data bus holders are disabled at reset. In
8-bit mode the bus holders can be enabled/disabled via the HBH bit of the BSCR. In 16-bit mode
the bus holders are always active on the HD7–HD0 pins.
I = Input, O = Output, Z = High-impedance, S = Supply
Although this pin includes an internal pulldown resistor, a 470- external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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