參數資料
型號： TMS320LF2407PZ
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數： 108/123頁
文件大小： 1205K
代理商： TMS320LF2407PZ
www.ti.com
Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21
12
18
17
14
13
SPISTE
(A)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
before the valid SPI clock edge and
remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 1)
108
Electrical Specifications
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