參數(shù)資料
型號: TMS320LF2406PZ
廠商: Texas Instruments, Inc.
英文描述: 1A, 52kHz (250khz Max) Current Mode PWM Control Circuit with 8.4V UVLO Threshold and 96% Max Duty Cycle<sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup> ; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
中文描述: DSP控制器
文件頁數(shù): 69/123頁
文件大?。?/td> 1205K
代理商: TMS320LF2406PZ
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 4-10. SPI-A Registers
NAME
SPICCR
SPICTL
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (X16)
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
(1)
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
SPI-A Baud Rate Register
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-11. SPI-B Registers
NAME
SPICCR
SPICTL
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
ADDRESS
0x7740
0x7741
0x7742
0x7744
0x7746
0x7747
0x7748
0x7749
0x774A
0x774B
0x774C
0x774F
SIZE (X16)
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
(1)
SPI-B Configuration Control Register
SPI-B Operation Control Register
SPI-B Status Register
SPI-B Baud Rate Register
SPI-B Receive Emulation Buffer Register
SPI-B Serial Input Buffer Register
SPI-B Serial Output Buffer Register
SPI-B Serial Data Register
SPI-B FIFO Transmit Register
SPI-B FIFO Receive Register
SPI-B FIFO Control Register
SPI-B Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Peripherals
69
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