參數(shù)資料
型號： TMS320LC5x
廠商： Texas Instruments, Inc.
英文描述： 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 96% Max Duty Cycle; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 92/123頁
文件大?。?/td> 1205K
代理商： TMS320LC5X
www.ti.com
t
h(boot-mode)(A)
t
w(RSL2)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
(Don’t Care)
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input
Peripheral/GPIO Function
t
d(EX)
OSCCLK * 5
OSCCLK/8
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 6-11. Reset (XRS) Timing Requirements
MIN
NOM
MAX
UNIT
cycles
cycles
t
w(RSL1)(1)
t
w(RSL2)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Pulse duration, reset pulse generated by
watchdog
Delay time, address/data valid after XRS high
Oscillator start-up time
Hold time for boot-mode pins
8t
c(OSCCLK)
8t
c(OSCCLK)
Warm reset
t
w(WDRS)
512t
c(OSCCLK)
cycles
t
d(EX)
t
OSCST(2)
t
h(boot-mode)
(1)
In addition to the t
requirement, XRS has to be low at least for 1 ms after V
DD
reaches 1.5 V.
(2)
Dependent on crystal/resonator and board design.
32t
c(OSCCLK)
cycles
ms
cycles
1
10
200t
c(OSCCLK)
A.
After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-6. Warm Reset
Figure 6-7
shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
92
Electrical Specifications
相關(guān)PDF資料
PDF描述
TMS320LC5X 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 96% Max Duty Cycle; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
TMS320LF2406PG 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 96% Max Duty Cycle; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
TMS320LF2406PGA 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 96% Max Duty Cycle; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
TMS320LF2406PGE DSP CONTROLLERS
TMS320LF2406PGEA DSP CONTROLLERS
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TMS320LF2402APGA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320LF2402APGAR 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320LF2402APGS 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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