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Contents
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Revision History
 ...........................................................................................................................
 8
1
Features
............................................................................................................................
 11
2
Introduction
.......................................................................................................................
 12
2.1
Pin Assignments
............................................................................................................
 13
2.2
Signal Descriptions
.........................................................................................................
 16
3
Functional Overview
...........................................................................................................
 22
3.1
Memory Map
................................................................................................................
 23
3.2
Brief Descriptions
...........................................................................................................
 27
3.2.1
C28x CPU
 .......................................................................................................
 27
3.2.2
Memory Bus (Harvard Bus Architecture)
 ....................................................................
 28
3.2.3
Peripheral Bus
 ..................................................................................................
 28
3.2.4
Real-Time JTAG and Analysis
 ................................................................................
 28
3.2.5
Flash
 ..............................................................................................................
 28
3.2.6
M0, M1 SARAMs
 ...............................................................................................
 29
3.2.7
L0, L1, H0 SARAMs
 ............................................................................................
 29
3.2.8
Boot ROM
 ........................................................................................................
 29
3.2.9
Security
 ..........................................................................................................
 30
3.2.10
Peripheral Interrupt Expansion (PIE) Block
..................................................................
 31
3.2.11
External Interrupts (XINT1, XINT2, XNMI)
...................................................................
 31
3.2.12
Oscillator and PLL
 ..............................................................................................
 31
3.2.13
Watchdog
 ........................................................................................................
 31
3.2.14
Peripheral Clocking
 .............................................................................................
 31
3.2.15
Low-Power Modes
 ..............................................................................................
 31
3.2.16
Peripheral Frames 0, 1, 2 (PFn)
 ..............................................................................
 32
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
 .........................................................
 32
3.2.18
32-Bit CPU-Timers (0, 1, 2)
 ...................................................................................
 32
3.2.19
Control Peripherals
 .............................................................................................
 32
3.2.20
Serial Port Peripherals
 .........................................................................................
 33
3.3
Register Map
................................................................................................................
 33
3.4
Device Emulation Registers
...............................................................................................
 36
3.5
Interrupts
 37
3.5.1
External Interrupts
 ..............................................................................................
 39
3.6
System Control
 .............................................................................................................
 40
3.6.1
OSC and PLL Block
 ............................................................................................
 41
3.6.2
Watchdog Block
 .................................................................................................
 44
3.7
Low-Power Modes Block
..................................................................................................
 45
4
Peripherals
........................................................................................................................
 46
4.1
32-Bit CPU-Timers 0/1/2
 ..................................................................................................
 46
4.2
Enhanced PWM Modules (ePWM1/2/3/4/5/6)
..........................................................................
 48
4.3
Hi-Resolution PWM (HRPWM)
...........................................................................................
 50
4.4
Enhanced CAP Modules (eCAP1/2/3/4)
 ................................................................................
 51
4.5
Enhanced QEP Modules (eQEP1/2)
.....................................................................................
 53
4.6
Enhanced Analog-to-Digital Converter (ADC) Module
 ................................................................
 55
4.7
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
.....................................
 60
4.8
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
....................................................
 65
4.9
Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
...........................................
 68
4.10
Inter-Integrated Circuit (I
2
C)
...............................................................................................
 72
4.11
GPIO MUX
..................................................................................................................
 74
5
Device Support
 ..................................................................................................................
 78
5.1
Device and Development Support Tool Nomenclature
................................................................
 78
2
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