參數(shù)資料
型號： TMS320LC2404PZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 24/123頁
文件大小： 1205K
代理商： TMS320LC2404PZ
www.ti.com
0x00 0000
Address
Data Space
M0 SARAM (1K 16)
0x00 0400
0x00 0800
0x00 0D00
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3F 7FF8
0x3F 8000
0x3F 9000
0x3F A000
0x3F F000
0x3F FFC0
OTP
(1 K 16, Secure Zone)
FLASH
(32 K 16, Secure Zone)
Boot ROM (4 K 16)
L
(
H
(
Reserved
M1 SARAM (1K 16)
L0 SARAM (0-wait)
(4k 16, Secure Zone, Dual Mapped)
L1 SARAM (0-wait)
(4k 16, Secure Zone, Dual Mapped)
L0 SARAM (0-wait) (4k 16,
L1 SARAM (0-wait) (4k 16,
Secure Zone, Dual Mapped)
128-bit Password
0x3F 0000
Prog Space
Peripheral Frame 0
Peripheral Frame 1
(protected)
Peripheral Frame 2
(protected)
PIE Vector RAM
(Ena (256 x 16)
Vectors (32 32)
(enabled if VMAP = 1, ENPIE = 0)
0x00 0E00
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
B.
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
“ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
C.
D.
Figure 3-3. F2806 Memory Map
24
Functional Overview
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