參數(shù)資料
型號: TMS320LC2404APZS
英文描述: DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 16位|的CMOS | QFP封裝| 100引腳|塑料
文件頁數(shù): 96/132頁
文件大小: 1707K
代理商: TMS320LC2404APZS
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
96
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PARAMETER MEASUREMENT INFORMATION
Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
SPISTE
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
Figure 41. SPI Master Mode External Timing (Clock Phase = 1)
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