參數(shù)資料
型號： TMS320LC2402PG
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 43/123頁
文件大小： 1205K
代理商： TMS320LC2402PG
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 3-14. PLLCR Register Bit Definitions
SYSCLKOUT
(CLKIN)
(2)
OSCCLK/2
OSCCLK
(OSCCLK*1)/2
(OSCCLK*2)/2
(OSCCLK*3)/2
(OSCCLK*4)/2
(OSCCLK*5)/2
(OSCCLK*6)/2
(OSCCLK*7)/2
(OSCCLK*8)/2
(OSCCLK*9)/2
(OSCCLK*10)/2
reserved
PLLCR[DIV]
(1)
PLLSTS[CLKINDIV]
0000 (PLL bypass)
0000 (PLL bypass)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
0
1
0
0
0
0
0
0
0
0
0
0
0
(1)
(2)
This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN.
CAUTION
PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be
changed once PLLSTS[CLKINDIV] is set.
The PLL-based clock module provides two modes of operation:
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-15. Possible PLL Configuration Modes
SYSCLKOUT
(CLKIN)
OSCCLK/2
PLL MODE
REMARKS
PLLSTS[CLKINDIV]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
PLL Off
1
OSCCLK
0
OSCCLK/2
PLL Bypass
1
OSCCLK
PLL Enable
0
OSCCLK*n/2
3.6.1.3
Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Functional Overview
43
相關(guān)PDF資料
PDF描述
TMS320LC2402PGE DSP CONTROLLERS
TMS320UVC5402PGE FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMS320C6202BPYP167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6711PZA167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PZA167 FIXED-POINT DIGITAL SIGNAL PROCESSORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320LC2404APZA 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 40MHZ 40MIPS 100LQFP - Trays
TMS320LC2406APZA 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 40MHZ 40MIPS 100LQFP - Trays
TMS320LC2406APZS 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 40MHZ 40MIPS 100LQFP - Trays
TMS320LC31PQ40 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320LC31PQL 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*