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參數(shù)資料
| 型號(hào)： | TMS320F2810PGFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 45/123頁(yè) |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320F2810PGFA |
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3.7
Low-Power Modes Block
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section
Section 3.7
,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
The low-power modes on the 280x are similar to the 240x devices.
Table 3-16
summarizes the various
modes.
Table 3-16. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT
(1)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
XRS, Watchdog interrupt, GPIO Port A
signal, debugger
(3)
, XNMI
IDLE
00
On
On
On
(2)
On
STANDBY
01
Off
Off
(watchdog still running)
Off
(oscillator and PLL turned off,
watchdog not functional)
XRS, GPIO Port A signal, XNMI,
debugger
(3)
HALT
1X
Off
Off
(1)
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(2)
(3)
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by
the processor. The LPM block performs no tasks during this mode as long as the
LPMCR0(LPM) bits are set to 0,0.
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK
before waking the device. The number of OSCCLKs is specified in the LPMCR0
register.
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device
from HALT mode. The user selects the signal in the GPIOLPMSEL register.
STANDBY Mode:
HALT Mode:
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed. See the
TMS320x280x System Control and Interrupts Reference Guide
(literature number SPRU712) for more details.
Functional Overview
45
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