參數(shù)資料
型號: TMS320F28069UPZT
廠商: Texas Instruments
文件頁數(shù): 124/174頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256KB FLASH 100LQFP
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Piccolo F2806x
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 90
系列: TMS320F2806x, Piccolo™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 50K x 16
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
NMIFLG[NMINT]
1
0
Generate
Interrupt
Pulse
When
Input = 1
NMINT
Latch
Clear
Set
Clear
NMIFLGCLR[NMINT]
XRS
0
NMICFG[CLOCKFAIL]
Latch
Clear
Set
Clear
XRS
NMIFLG[CLOCKFAIL]
NMI Watchdog
SYSCLKOUT
SYSRS
NMIRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
NMIFLGCLR[CLOCKFAIL]
SYNC?
NMIFLGFRC[CLOCKFAIL]
SYSCLKOUT
See System
Control Section
CLOCKFAIL
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
2.9.5
Loss of Input Clock (NMI Watchdog Function)
The
2806x
devices
may
be
clocked
from
either
one
of
the
internal
zero-pin
oscillators
(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the
clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will
issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at
a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired
immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the
Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect
the input clock failure and initiate necessary corrective action such as switching over to an alternative
clock source (if available) or initiate a shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 2-15 shows the interrupt mechanisms involved.
Figure 2-15. NMI-Watchdog
2.9.6
CPU-Watchdog Module
The CPU-watchdog module on the 2806x device is similar to the one used on the 281x/280x/283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter
or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets
the watchdog counter. Figure 2-16 shows the various functional blocks within the watchdog module.
Copyright 2010–2012, Texas Instruments Incorporated
Device Overview
53
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