參數(shù)資料
型號(hào): TMS320F2801X
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 34/140頁
文件大?。?/td> 1108K
代理商: TMS320F2801X
www.ti.com
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007
Table 3-4. Addresses of Flash Sectors in F2801, F28015, F28016
ADDRESS RANGE
0x3F 4000 - 0x3F 4FFF
0x3F 5000 - 0x3F 5FFF
0x3F 6000 - 0x3F 6FFF
0x3F 7000 - 0x3F 7F7F
0x3F 7F80 - 0x3F 7FF5
PROGRAM AND DATA SPACE
Sector D (4K x 16)
Sector C (4K x 16)
Sector B (4K x 16)
Sector A (4K x 16)
Program to 0x0000 when using the
Code Security Module
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
0x3F 7FF6 - 0x3F 7FF7
0x3F 7FF8 - 0x3F 7FFF
NOTE
When the code-security passwords are programmed, all addresses between
0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may
be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and
should not contain program code. .
On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF are
reserved for TI, irrespective of whether code security has been used or not. User
application should not use these locations in any way.
Table 3-5
shows how to handle these memory locations.
Table 3-5. Impact of Using the Code Security Module
ADDRESS
FLASH
ROM
Code security enabled
Code security disabled
Application code and data
Reserved for data only
Code security enabled
Fill with 0x0000
Code security disabled
Application code and data
0x3F7F80 - 0x3F7FEF
0x3F7FF0 - 0x3F7FF5
0x3D7BFC – 0x3D7BFF
Fill with 0x0000
Reserved for TI. Do not use.
Application code and data
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in
Table 3-6
.
34
Functional Overview
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