參數(shù)資料
型號： TMS320F241PGE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 97/123頁
文件大?。?/td> 1205K
代理商： TMS320F241PGE
www.ti.com
t
w(WAKE-INT)
t
d(WAKE-STBY)
t
d(IDLEXCOL)
Wakeup
Signal
X1/X2 or
X1 or
XCLKIN
XCLKOUT
STANDBY
Normal Execution
STANDBY
Flushing Pipeline
(A)
(B)
(C)
(D)
(E)
(F)
Device
Status
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 6-17. STANDBY Mode Switching Characteristics
PARAMETER
Delay time, IDLE instruction ex-
ecuted to XCLKOUT low
Delay time, external wake signal
to program execution resume
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
d(IDLE-XCOL)
32t
c(SCO)
45t
c(SCO)
cycles
cycles
Without input qualifier
100t
c(SCO)
Wake up from flash
–
Flash module in active
state
cycles
With input qualifier
100t
c(SCO)
+ t
w(WAKE-INT)
t
d(WAKE-STBY)
Without input qualifier
1125t
c(SCO)
Wake up from flash
–
Flash module in sleep
state
cycles
With input qualifier
1125t
c(SCO)
+ t
w(WAKE-INT)
Without input qualifier
With input qualifier
100t
c(SCO)
cycles
Wake up from SARAM
100t
c(SCO)
+ t
w(WAKE-INT)
(1)
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
A.
B.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
C.
D.
E.
F.
Figure 6-12. STANDBY Entry and Exit Timing Diagram
Electrical Specifications
97
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