參數(shù)資料
型號(hào): TMS320DM647ZUT7
廠商: Texas Instruments
文件頁(yè)數(shù): 9/190頁(yè)
文件大?。?/td> 0K
描述: IC DGTL MEDIA PROC 529-FCBGA
標(biāo)準(zhǔn)包裝: 84
系列: TMS320DM64x, DaVinci™
類型: 定點(diǎn)
接口: 主機(jī)接口,I²C,McASP,PCI,SPI,UART
時(shí)鐘速率: 720MHz
非易失內(nèi)存: ROM(64 kB)
芯片上RAM: 320kB
電壓 - 輸入/輸出: 1.8V,3.3V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 529-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 529-FCBGA(19x19)
包裝: 托盤
其它名稱: 296-34539-5
TMS320DM647ZUT7-ND
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SPRS372H – MAY 2007 – REVISED APRIL 2012
NOTE
The region (see Figure 6-14) should encompass all DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the
DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they are
routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the 1.8-V power plane
should cover the entire keep out region.
6.9.3.6
Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 6-33 contains the minimum numbers and capacitance required for the bulk bypass capacitors. This
table covers only the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass capacitance
may be needed for other circuitry.
Table 6-33. Bulk Bypass Capacitors
NO.
PARAMETER
MIN
MAX
UNIT
1
DVDD18 Bulk Bypass Capacitor Count
(1)
3
Devices
2
DVDD18 Bulk Bypass Total Capacitance
30
μF
3
DDR#1 Bulk Bypass Capacitor Count(2)
1
Devices
4
DDR#1 Bulk Bypass Total Capacitance
10
μF
5
DDR#2 Bulk Bypass Capacitor Count(2) (3)
1
Devices
6
DDR#2 Bulk Bypass Total Capacitance(3)
10
μF
(1)
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(2)
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(3)
Only used on 32-bit wide DDR2 memory systems
6.9.3.7
High-Speed Bypass Capacitors
High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and
DSP/DDR ground connections. Table 6-34 contains the specification for the HS bypass capacitors as well
as for the power connections on the PCB.
6.9.3.8
Net Classes
Table 6-35 lists the clock net classes for the DDR2 interface. Table 6-36 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 6-34. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
MAX
UNIT
1
HS Bypass Capacitor Package Size(1)
0402
10 Mils
2
Distance from HS bypass capacitor to device being bypassed
250
Mils
3
Number of connection vias for each HS bypass capacitor(2)
2
Vias
4
Trace length from bypass capacitor contact to connection via
1
30
Mils
5
Number of connection vias for each DDR2 device power or ground balls
1
Vias
6
Trace length from DDR2 device power ball to connection via
35
Mils
7
DVDD18 HS Bypass Capacitor Count
(3)
20
Devices
8
DVDD18 HS Bypass Capacitor Total Capacitance
1.2
μF
(1)
L × W, 10 mil units ( i.e., a 0402 is a 40 × 20 mil surface mount capacitor)
(2)
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3)
These devices should be placed as close as possible to the device being bypassed.
106
Peripheral Information and Electrical Specifications
Copyright 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TMS320DM647 TMS320DM648
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