參數(shù)資料
型號： TMS320DM647_08
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 97/167頁
文件大?。?/td> 1438K
代理商： TMS320DM647_08
www.ti.com
P
5
6
2
AECLKIN
AECLKOUT1
4
4
1
3
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372A–MAY 2007–REVISED JUNE 2007
Table 6-30. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the
EMIFA Module
(1)(2)(3)
(see
Figure 6-14
)
-720
-900
NO.
PARAMETER
UNIT
MIN
MAX
E + 0.7
EH + 0.7
EL + 0.7
1
2
3
4
5
6
t
c(EKO)
t
w(EKOH)
t
w(EKOL)
t
t(EKO)
t
d(EKIH-EKOH)
t
d(EKIL-EKOL)
Cycle time, AECLKOUT
Pulse duration, AECLKOUT high
Pulse duration, AECLKOUT low
Transition time, AECLKOUT
Delay time, AECLKIN high to AECLKOUT high
Delay time, AECLKIN low to AECLKOUT low
E – 0.7
EH – 0.7
EL – 0.7
ns
ns
ns
ns
ns
ns
1
8
8
1
1
(1)
(2)
(3)
E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
A.
B.
C.
E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns
for EMIFA.
Figure 6-14. AECLKOUT Timing for the EMIFA Module
6.10.3.1
Asynchronous Memory Timing
Table 6-31. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(1)(2)(3)
(see
Figure 6-15
and
Figure 6-16
)
-720
-900
MIN
6.5
3
1
2
2E + 5
NO.
UNIT
MAX
3
4
5
6
7
t
su(EDV-AOEH)
t
h(AOEH-EDV)
t
su(ARDY-EKOH)
t
h(EKOH-ARDY)
t
w(ARDY)
Setup time, AEDx valid before AAOE high
Hold time, AEDx valid after AAOE high
Setup time, AARDY valid before AECLKOUT low
Hold time, AARDY valid after AECLKOUT low
Pulse width, AARDY assertion and deassertion
Delay time, from AARDY sampled deasserted on AECLKOUT falling to
beginning of programmed hold period
Setup time, before end of programmed strobe period by which AARDY
should be asserted in order to insert extended strobe wait states.
ns
ns
ns
ns
ns
8
t
d(ARDY-HOLD)
4E
ns
9
t
su(ARDY-HOLD)
2E
ns
(1)
(2)
(3)
E = AECLKOUT period in ns for EMIFA
To specify data setup time, simply program the strobe width wide enough.
AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E
to specify setup and hold time is met.
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Peripheral Information and Electrical Specifications
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TMS320DM647CUTA8 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM647CUTD7 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM647ZUT1 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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