參數(shù)資料
型號： TMS320DM642GDK500
廠商： Texas Instruments, Inc.
英文描述： Adjustable 2.5-36V +/-2.2% Tolerance, 1-100mA Shunt Regulator - PB Free; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
中文描述： 視頻/影像定點數(shù)字信號處理器
文件頁數(shù)： 73/123頁
文件大小： 1205K
代理商： TMS320DM642GDK500
www.ti.com
SYSRS
Data[16]
SYSCLKOUT
Data[16]
Addr[16]
Control
I2CINT1A
I2CINT2A
C28X CPU
GPIO
MUX
I
2
CA
System Control
Block
I2CAENCLK
PIE
Block
SDAA
SCLA
P
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
The I
2
C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I
2
C port are
also at the SYSCLKOUT rate.
The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I
2
C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
B.
Figure 4-15. I
2
C Peripheral Module Interfaces
The registers in
Table 4-14
configure and control the I
2
C port operation.
Table 4-14. I
2
C-A Registers
NAME
I2COAR
I2CIER
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
-
DESCRIPTION
I
2
C own address register
I
2
C interrupt enable register
I
2
C status register
I
2
C clock low-time divider register
I
2
C clock high-time divider register
I
2
C data count register
I
2
C data receive register
I
2
C slave address register
I
2
C data transmit register
I
2
C mode register
I
2
C interrupt source register
I
2
C prescaler register
I
2
C FIFO transmit register
I
2
C FIFO receive register
I
2
C receive shift register (not accessible to the CPU)
I
2
C transmit shift register (not accessible to the CPU)
Peripherals
73
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