參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 18/158頁
文件大小： 1319K
代理商： TMS320DM355_07
www.ti.com
P
2.4.3
Asynchronous External Memory Interface (AEMIF)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 2-8. Analog Video Terminal Functions
TERMINAL
TYPE
(1)
OTHER
(2)
DESCRIPTION
NAME
NO.
Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not
used, the VREF signal should be connected to V
SS
.
Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not
used, the IOUT signal should be connected to V
SS
.
Video DAC: External resistor (2550 Ohms to GND) connection for current bias
configuration. When the DAC is not used, the IBIAS signal should be connected to
V
SS
.
Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to
TVOUT). When the DAC is not used, the VFB signal should be connected to V
SS
.
Video DAC: Analog Composite NTSC/PAL output (See
Figure 5-31
and
Figure 5-32
for
circuit connection). When the DAC is not used, the TVOUT signal should be left as a
No Connect or connected to V
SS
.
Video DAC: Analog 1.8V power. When the DAC is not used, the V
DDA18_DAC
signal
should be connected to V
SS
.
Video DAC: Analog 1.8V ground. When the DAC is not used, the V
SSA_DAC
signal
should be connected to V
SS
.
VREF
J7
A I/O/Z
IOUT
E1
A I/O/Z
IBIAS
F2
A I/O/Z
VFB
G1
A I/O/Z
TVOUT
F1
A I/O/Z
V
V
DDA18_DAC
L7
PWR
V
SSA_DAC
L8
GND
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply
voltage for each signal. See
Section 5.3
,
Power Supplies
for more detail.
PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k
resistor should be used.)
(2)
The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND.
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Address bus bit[13]
GIO: GIO[67]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used
to drive boot status LED signal (active low) in ROM boot modes.
Async EMIF: Address bus bit[12]
GIO: GIO[66]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
Async EMIF: Address bus bit[11]
GIO: GIO[65]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets
default for PinMux2_EM_D15_8: AEMIF default bus width (16 or 8 bits)
Async EMIF: Address bus bit[10]
GIO: GIO[64]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit[09]
GIO: GIO[63]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit[08]
GIO: GIO[62]
AECFG[0] sets default for:
PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND)
PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND)
Async EMIF: Address bus bit[07]
GIO: GIO[61]
EM_A13/
GIO067/
BTSEL[1]
PD
V
DD
V19
I/O/Z
EM_A12/
GIO066/
BTSEL[0]
PD
V
DD
U19
I/O/Z
EM_A11/
GIO065/
AECFG[3]
PU
V
DD
R16
I/O/Z
EM_A10/
GIO064/
AECFG[2]
PU
V
DD
R18
I/O/Z
EM_A09/
GIO063/
AECFG[1]
PD
V
DD
P17
I/O/Z
EM_A08/
GIO062/
AECFG[0]
PD
V
DD
T19
I/O/Z
EM_A07/
GIO061
P16
I/O/Z
V
DD
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
Specifies the operating I/O supply voltage for each signal. See
Section 5.3
,
Power Supplies
for more detail.
PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k
resistor should be used.)
Device Overview
18
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