![](http://datasheet.mmic.net.cn/220000/TMS320F2801GGMS_datasheet_15506372/TMS320F2801GGMS_34.png)
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 3-6. Peripheral Frame 0 Registers
(1)(2)
NAME
ADDRESS RANGE
0x0880
0x09FF
0x0A80
0x0ADF
0x0AE0
0x0AEF
0xB00
0xB0F
0x0C00
0x0C3F
0x0CE0
0x0CFF
0x0D00
0x0DFF
SIZE (x16)
ACCESS TYPE
(3)
Device Emulation Registers
384
EALLOW protected
EALLOW protected
CSM Protected
FLASH Registers
(4)
96
Code Security Module Registers
16
EALLOW protected
ADC Result Registers
(dual-mapped)
16
Not EALLOW protected
CPU-TIMER0/1/2 Registers
64
Not EALLOW protected
PIE Registers
32
Not EALLOW protected
PIE Vector Table
256
EALLOW protected
(1)
(2)
(3)
Registers in Frame 0 support 16-bit and 32-bit accesses.
Missing segments of memory space are reserved and should not be used in applications.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
(4)
34
Functional Overview