參數(shù)資料
    

    


    


    
型號：
TMS320C6711GLW150

    

    
廠商：
Texas Instruments, Inc.

    

    
元件分類：
數(shù)字信號處理

    

    
英文描述：
FIXED-POINT DIGITAL SIGNAL PROCESSORS

    

    
中文描述：
定點(diǎn)數(shù)字信號處理器

    

    
文件頁數(shù)：
17/123頁

    

    
文件大?。?/td>
1205K

    

    
代理商：
TMS320C6711GLW150


    

    

    

	
    
    
    

    
    
	
    www.ti.com
    TMS320F2808, TMS320F2806
    TMS320F2801, UCD9501
    Digital Signal Processors
    SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
    Table 2-2. Signal Descriptions
    PIN NO.
    NAME
    DESCRIPTION
    (1)
    PZ PIN
    #
    GGM
    BALL #
    JTAG
    JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
    the operations of the device. If this signal is not connected or driven low, the device operates in its
    functional mode, and the test reset signals are ignored.
    NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
    high test pin and must be maintained low at all times during normal device operation. In a low-noise
    environment, TRST may be left floating. In other instances, an external pulldown resistor is
     highly
    recommended
    . The value of this resistor should be based on drive strength of the debugger pods
    applicable to the design. A 2.2-k
     resistor generally offers adequate protection. Since this is
    application-specific, it is recommended that each target board is validated for proper operation of
    the debugger and the application. (I,
     ↓
    )
    JTAG test clock with internal pullup (I,
     ↑
    )
    JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
    controller on the rising edge of TCK. (I,
     ↑
    )
    JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
    or data) on a rising edge of TCK. (I,
     ↑
    )
    JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
    are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
    Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
    system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive
     ↑
    )
    Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
    system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive,
     ↑
    )
    FLASH
    3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
    Test Pin. Reserved for TI. Must be left unconnected. (I/O)
    Test Pin. Reserved for TI. Must be left unconnected. (I/O)
    CLOCK
    Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
    frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
    (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
    can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
    placed in high-impedance state during a reset. (O/Z, 8 mA drive).
    External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
    the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is
    used to feed clock to X1 pin), this pin must be tied to GND. (I)
    Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
    resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
    power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
    pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
    be tied to GND. (I)
    Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
    X2. If X2 is not used it must be left unconnected. (O)
    RESET
    Device Reset (in) and Watchdog Reset (out).
    Device reset. XRS causes the device to terminate execution. The PC will point to the address
    contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
    location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
    During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
    cycles. (I/OD,
     ↑
    )
    The output buffer of this pin is an open-drain with an internal pullup (100
     μ
    A, typical). It is
    recommended that this pin be driven by an open-drain device.
    ADC SIGNALS
    ADC Group A, Channel 7 input (I)
    ADC Group A, Channel 6 input (I)
    TRST
    84
    A6
    TCK
    75
    A10
    TMS
    74
    B10
    TDI
    73
    C9
    TDO
    76
    B9
    EMU0
    80
    A8
    EMU1
    81
    B7
    VDD3VFL
    TEST1
    TEST2
    96
    97
    98
    C4
    A3
    B3
    XCLKOUT
    66
    E8
    XCLKIN
    90
    B5
    X1
    88
    E6
    X2
    86
    C6
    XRS
    78
    B8
    ADCINA7
    ADCINA6
    16
    17
    F3
    F4
    (1)
    I = Input, O = Output, Z = High impedance, OD = Open drain,
     ↑
     = Pullup,
     ↓
     = Pulldown
    Introduction
    17
    
    
    
    
    
    


    


    

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