參數(shù)資料
型號： TMS320C6415TBGLZ1
廠商： Texas Instruments
文件頁數(shù)： 86/146頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 1.0GHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應商設備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only]
(CONTINUED)
HAS/PPAR§
T3
I/O/Z
Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR§
R2
I/O/Z
Host chip select (I) [default] or PCI parity error (I/O/Z)
HDS1/PSERR§
T1
I/O/Z
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
HDS2/PCBE1§
T2
I/O/Z
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
HRDY/PIRDY§
P4
I/O/Z
Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
HD31/AD31§
J2
HD30/AD30§
K3
HD29/AD29§
J1
HD28/AD28§
K4
HD27/AD27§
K2
HD26/AD26§
L3
HD25/AD25§
K1
HD24/AD24§
L4
HD23/AD23§
L1
HD22/AD22§
M4
Host-port data (I/O/Z) [default] (C64x) or PCI data-address bus (I/O/Z) [C6415T and C6416T]
HD21/AD21§
M2
As HPI data bus (PCI_EN pin = 0)
HD20/AD20§
N4
As HPI data bus (PCI_EN pin = 0)
Used for transfer of data, address, and control
HD19/AD19§
M1
Used for transfer of data, address, and control
Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/pulldown
resistor on the HD5 pin:
HD18/AD18§
N5
resistor on the HD5 pin:
HD17/AD17§
N1
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
HD16/AD16§
P5
I/O/Z
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
HD15/AD15§
U4
I/O/Z
reserved pins in the high-impedance state.)
HD14/AD14§
U1
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD13/AD13§
U3
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD12/AD12§
U2
As PCI data-address bus (PCI_EN pin = 1) [C6415T and C6416T devices only]
HD11/AD11§
V4
As PCI data-address bus (PCI_EN pin = 1) [C6415T and C6416T devices only]
Used for transfer of data and address
HD10/AD10§
V1
Used for transfer of data and address
The C6414T device does not support the PCI peripheral; therefore, the HPI peripheral pins are
HD9/AD9§
V3
The C6414T device does not support the PCI peripheral; therefore, the HPI peripheral pins are
standalone peripheral functions, not muxed.
HD8/AD8§
V2
standalone peripheral functions, not muxed.
HD7/AD7§
W2
HD6/AD6§
W4
HD5/AD5§
Y1
HD4/AD4§
Y3
HD3/AD3§
Y2
HD2/AD2§
Y4
HD1/AD1§
AA1
HD0/AD0§
AA3
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
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