參數資料
型號: TMS320C6414TGLZ7
廠商: Texas Instruments
文件頁數: 115/146頁
文件大?。?/td> 0K
描述: IC DSP FIXED-POINT 532-FCBGA
標準包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點
接口: 主機接口,McBSP,PCI,UTOPIA
時鐘速率: 720MHz
非易失內存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,FCBGA
供應商設備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱: 296-17757
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
70
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
power-down mode logic
Figure 9 shows the power-down mode logic on the C6414T/C6415T/C6416T.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN
RESET
CLKOUT6
PD3
Internal
Peripherals
CLKOUT4
Clock
and Dividers
Distribution
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
TMS320C6414T/15T/16T
Figure 9. Power-Down Mode Logic
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 1510)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10 and described in Table 32.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
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