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  • 參數(shù)資料
    型號: TMS320C6211PQ150
    廠商: Texas Instruments, Inc.
    元件分類: 數(shù)字信號處理
    英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
    中文描述: 定點數(shù)字信號處理器
    文件頁數(shù): 112/123頁
    文件大?。?/td> 1205K
    代理商: TMS320C6211PQ150
    www.ti.com
    6.9.7.3
    Sequential Sampling Mode (Single-Channel) (SMODE = 0)
    Analog Input on
    Channel Ax or Bx
    ADC Clock
    Sample and Hold
    SH Pulse
    SMODE Bit
    t
    dschx_n
    t
    dschx_n+1
    Sample n
    Sample n+1
    Sample n+2
    t
    SH
    ADC Event Trigger from
    ePWM or Other Sources
    t
    d(SH)
    TMS320F2808, TMS320F2806
    TMS320F2801, UCD9501
    Digital Signal Processors
    SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
    In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
    to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
    external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
    every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
    below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
    selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
    width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
    Figure 6-23. Sequential Sampling Mode (Single-Channel) Timing
    Table 6-39. Sequential Sampling Mode Timing
    SAMPLE n
    SAMPLE n + 1
    AT 12.5 MHz
    ADC CLOCK,
    t
    c(ADCCLK)
    = 80 nS
    REMARKS
    t
    d(SH)
    Delay time from event trigger to
    sampling
    Sample/Hold width/Acquisition
    Width
    Delay time for first result to appear
    in Result register
    Delay time for successive results to
    appear in Result register
    2.5t
    c(ADCCLK)
    t
    SH
    (1 + Acqps) *
    t
    c(ADCCLK)
    4t
    c(ADCCLK)
    80 ns with Acqps = 0
    Acqps value = 0-15
    ADCTRL1[8:11]
    t
    d(schx_n)
    320 ns
    t
    d(schx_n+1)
    (2 + Acqps) *
    t
    c(ADCCLK)
    160 ns
    112
    Electrical Specifications
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