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參數(shù)資料
| 型號(hào)： | TMS320C6211PJA167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 110/123頁(yè) |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320C6211PJA167 |
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6.9.7.1
ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
PWDNADC
Request for
ADC
Conversion
t
d(BGR)
t
d(PWD)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Figure 6-21. ADC Power-Up Control Bit Timing
Table 6-37. ADC Power-Up Delays
PARAMETER
(1)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
MIN
TYP
5
MAX
UNIT
ms
t
d(BGR)
t
d(PWD)
20
50
μ
s
ms
1
(1)
Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waiting
t
d(BGR)
ms before first conversion.
Table 6-38. Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)
(1)(2)
ADC OPERATING MODE
Mode A (Operational Mode):
CONDITIONS
V
DDA18
30
V
DDA3.3
2
UNIT
mA
BG and REF enabled
PWD disabled
Mode B:
9
0.5
ma
ADC clock enabled
BG and REF enabled
PWD enabled
Mode C:
5
20
μ
A
ADC clock enabled
BG and REF disabled
PWD enabled
Mode D:
5
15
μ
A
ADC clock disabled
BG and REF disabled
PWD enabled
(1)
Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
V
DDA18
includes current into V
DD1A18
and V
DD2A18
. V
DDA3.3
includes current into V
DDA2
and V
DDAIO
.
(2)
110
Electrical Specifications
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