參數(shù)資料
型號: TMS320C6211J100
廠商: Texas Instruments, Inc.
英文描述: 4 #18 PVC PVC RoHS Compliant: Yes
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 104/123頁
文件大?。?/td> 1205K
代理商: TMS320C6211J100
www.ti.com
9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
8
5
3
2
1
SPISTE
(A)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
In the master mode, SPISTE goes active 0.5t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-17. SPI Master Mode External Timing (Clock Phase = 0)
104
Electrical Specifications
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