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參數(shù)資料
| 型號(hào)： | TMS320C6211GLZ167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 76/123頁(yè) |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320C6211GLZ167 |
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www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 4-16. F2808 GPIO MUX Table
DEFAULT AT RESET
PRIMARY I/O FUNC-
TION
(GPxMUX1/2 BITS =
0,0)
GPAMUX1/2
(1)
REGISTER
BITS
PERIPHERAL SELECTION
1
(2)
(GPxMUX1/2 BITS = 0,1)
PERIPHERAL SELECTION 2
(GPxMUX1/2 BITS = 1,0)
PERIPHERAL SELECTION 3
(GPxMUX1/2 BITS = 1,1)
GPAMUX1
1-0
3-2
5-4
7-6
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
TZ2 (I)
TZ3 (I)
TZ4 (I)
Reserved
(3)
SPISIMOD (I/O)
Reserved
(3)
SPISOMID (I/O)
Reserved
(3)
SPICLKD (I/O)
EPWMSYNCI (I)
SPISTED (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
Reserved
(3)
Reserved
(3)
Reserved
(3)
Reserved
(3)
Reserved
(3)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
ADCSOCAO (O)
ECAP3 (I/O)
ADCSOCBO (O)
ECAP4 (I/O)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
GPAMUX2
1-0
3-2
5-4
7-6
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
Reserved
(3)
Reserved
(3)
Reserved
(3)
Reserved
(3)
TZ5 (I)
TZ6 (I)
Reserved
(3)
Reserved
(3)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ5 (I)
TZ6 (I)
Reserved
(3)
Reserved
(3)
GPBMUX1
1-0
3-2
5-4
GPIO32
GPIO33
GPIO34
SDAA (I/OC)
SCLA (I/OC
)
Reserved
(3)
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved
(3)
ADCSOCAO (O)
ADCSOCBO (O)
Reserved
(3)
(1)
(2)
GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
This table pertains to the 2808 device. Some peripherals may not be available in the 2806 or 2801 devices. See the pin descriptions for
more detail.
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(3)
76
Peripherals
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