參數(shù)資料
型號(hào)： TMS320C6211GLWA150
廠商： Texas Instruments, Inc.
英文描述： HEADER 10X1, 0.156 SINGLE ROW STRAIGHT FRICTION LOCK
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 27/123頁
文件大?。?/td> 1205K
代理商： TMS320C6211GLWA150
www.ti.com
3.2
Brief Descriptions
3.2.1
C28x CPU
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the
code-security passwords are programmed. If security is not a concern, addresses
0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 –
0x3F7FF5 are reserved for data variables and should not contain program code.
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.
The wait states for the various spaces in the memory map area are listed in
Table 3-4
.
Table 3-4. Wait States
AREA
WAIT-STATES
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait
COMMENTS
Fixed
Fixed
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Fixed. The eCAN peripheral can extend a cycle as needed.
Peripheral Frame 2
Fixed
L0 & L1 SARAMs
Programmed via the Flash registers. 1-wait-state operation
is possible at a reduced CPU frequency. See Section
Section 3.2.5
for more information.
Programmed via the Flash registers. 0-wait-state operation
is possible at reduced CPU frequency. The CSM password
locations are hardwired for 16 wait-states. See Section
Section 3.2.5
for more information.
Fixed
Fixed
Programmable,
1-wait minimum
OTP
Programmable,
0-wait minimum
Flash
H0 SARAM
Boot-ROM
0-wait
1-wait
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is a
very efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in
a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.
Functional Overview
27
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