www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 6-32. SPI Master Mode External Timing (Clock Phase = 0)
(1)(2)(3)(4)(5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
MIN
4t
c(LCO)
0.5t
c(SPC)M
-10
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
MIN
5t
c(LCO)
0.5t
c(SPC)M
- 0.5t
c(LCO)
- 10
UNIT
MAX
MAX
1
2
t
c(SPC)M
t
w(SPCH)M
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low
(clock polarity = 1)
Pulse duration, SPICLK low
(clock polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
128t
c(LCO)
0.5t
c(SPC)M
127t
c(LCO)
ns
ns
0.5t
c(SPC)
M - 0.5t
c(LCO)
t
w(SPCL)M
0.5t
c(SPC)M
- 10
0.5t
c(SPC)M
0.5t
c(SPC)M
- 0.5t
c(LCO)
- 10
0.5t
c(SPC)M
- 0.5t
c(LCO)
3
t
w(SPCL)M
0.5t
c(SPC)M
- 10
0.5
tc(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
-10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
ns
t
w(SPCH)M
0.5
tc(SPC)M
- 10
0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
- 10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
4
t
d(SPCH-SIMO)M
10
10
ns
t
d(SPCL-SIMO)M
10
10
5
t
v(SPCL-SIMO)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
-10
t
v(SPCH-SIMO)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
-10
8
t
su(SOMI-SPCL)M
35
35
ns
t
su(SOMI-SPCH)M
35
35
ns
9
t
v(SPCL-SOMI)M
0.25t
c(SPC)M
-10
0.5t
c(SPC)M
- 0.5t
c(LCO)
- 10
t
v(SPCH-SOMI)M
0.25t
c(SPC)M
- 10
0.5t
c(SPC)M
- 0.5t
c(LCO)
- 10
ns
(1)
(2)
(3)
(4)
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
t
= LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
(5)
Electrical Specifications
103