參數(shù)資料
型號： TMS320C6211GGUA120
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 33/123頁
文件大小： 1205K
代理商： TMS320C6211GGUA120
www.ti.com
3.2.20
Serial Port Peripherals
3.3
Register Map
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
eQEP:
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic
to identify simultaneous edge transition in QEP signals.
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
ADC:
The 280x devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the 280x, the SPI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the 280x, the SCI contains a 16-level receive and transmit FIFO for
reducing interrupt servicing overhead.
The inter-integrated circuit (I
2
C) module provides an interface between a DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I
2
C-bus) specification version
2.1 and connected by way of an I
2
C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSP through the I
2
C module.
On the 280x, the I
2
C contains a 16-level receive and transmit FIFO for reducing interrupt
servicing overhead.
SPI:
SCI:
I
2
C:
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
Peripheral
Frame 1
Peripheral
Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See
Table 3-6
These are peripherals that are mapped to the 32-bit peripheral bus.
See
Table 3-7
These are peripherals that are mapped to the 16-bit peripheral bus.
See
Table 3-8
Functional Overview
33
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