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參數(shù)資料
| 型號： | TMS320C6211FN150 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 8/123頁 |
| 文件大小： | 1205K |
| 代理商： | TMS320C6211FN150 |
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Revision History
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
This data manual was revised from SPRS230E to SPRS230F. Substantial additions and changes were
made to the electrical specifications section.
Scope:
this document has been reviewed for technical accuracy; the technical content is up to date as of
the specified release date with the following changes:
Technical Changes Made for Revision F
Location
Global:
Additions, Deletions, Changes
Changed from Advance Information to Production Data.
Extensive changes were made to the electrical specifications section, including addition of several
new sections.
Changed SCIRXB to SCIRXDB and SCITXB to SCITXDB to be consistent with SCIRXDA, etc.
Added package designators to temperature options on features page
Added information on UCD9501 device nomenclature to Note 2 of the hardware features table and
modified other parts of the table
Modified pinouts for F2808 and F2806, correcting some GPIO options
Modified the descriptions of TRST, XCLKOUT, XCLKIN, X1, ADCREFM, and ADCREFP pins
Added information on addresses 0x3F7FF0 - 0x3F7FF5 that are reserved for data variables and
changed the note
Added a note about programming code security to the three flash sector address tables
Changed 12-bit ADC Registers to ADC Result Registers (dual mapped)
Added ADC Result Registers
Modified PartID and RevID information
Added a reserved address to the F2808 memory map
Changed the note about programming code under Code Security
Modified the Boot ROM address in the memory maps for the F2806, F2801, and UCD9501 devices.
Modified description of security and password protection
Modified ADC description
Added a row to the Peripheral Frame 0 registers table for ADC Result Registers
Modified Device Emulation Registers table
Modified the Clock and Reset Domains figure
Modified the descriptions for the XCLK, HISPCP, and LOSPCP registers
Modified the OSC and PLL Block Diagram
Changed the description of the OSC and PLL block
Split the recommended crystal/clock connection figure into two figures - Using the Internal Oscillator
and Using a 3.3-V External Oscillator - and added a third figure, Using a 1.8-V External Oscillator
Modified the PLLCR Register Bit Definitions table
Modified the Possible PLL Configuration Modes table
Modified description in section on Loss of Input Clock
Modified the Low-Power Modes table
Changed HiRes to HRPWM in the ePWM Control and Status Registers table
Modified the Multiple PWM Modules in a System table
Modified ADC Pin Connections With Internal Reference figure
Modified the Serial Peripheral Interface (SPI) features list by deleting the sentence following the baud
rate equations
Added F2808 GPIO MUX Table
Added a figure to show device nomenclature for the UCD family
Changed values in the Absolute Maximum Ratings table and added junction temperature range
Modified the Recommended Operating Conditions table
Section 1
Table 2-1
Figure 2-1
Table 2-2
Section 3.2.5
Table 3-1
-
Table 3-3
Section 3.2.16
Table 3-6
Section 3.4
Figure 3-2
Section 3.2.9
Figure 3-3
and
Figure 3-4
Section 3.2.9
Section 3.2.16
Table 3-6
Table 3-9
Figure 3-7
Table 3-13
Figure 3-8
Section 3.6.1
Figure 3-11
Table 3-14
Table 3-15
Section 3.6.1.3
Table 3-16
Table 4-2
Figure 4-3
Figure 4-8
Section 4.9
Table 4-16
Figure 5-2
Section 6.1
Section 6.2
8
Revision History
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