參數資料
型號: TMS320C6203CGNZ250
英文描述: DSP|32-BIT|CMOS|BGA|352PIN|PLASTIC
中文描述: 數字信號處理器| 32位|的CMOS | BGA封裝| 352PIN |塑料
文件頁數: 86/132頁
文件大小: 1707K
代理商: TMS320C6203CGNZ250
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
86
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
low-power mode timings
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 29, Figure 30, and Figure 31)
PARAMETER
LOW-POWER MODES
IDLE1
MIN
TYP
MAX
UNIT
td(WAKE-A)
Delay time, CLKOUT switching to
program execution resume
LPM0
12
×
tc(CO)
15
×
tc(CO)
ns
IDLE2
LPM1
td(IDLE-COH)
Delay time, Idle instruction executed to
CLKOUT high
IDLE2
LPM1
4tc(CO)
ns
td(WAKE-OSC)
Delay time, wakeup interrupt
asserted to oscillator running
HALT
{PLL/OSC power down}
LPM2
OSC start-up
and PLL lock
time
ms
td(IDLE-OSC)
Delay time, Idle instruction executed to
oscillator power off
4tc(CO)
ns
td(EX)
Delay time, reset vector executed after RS high
36H
ns
WAKE INT
CLKOUT
A0
A15
td(WAKE
A)
WAKE INT can be any valid interrupt or RESET.
Figure 29. IDLE1 Entry and Exit Timing
LPM0
td(WAKE
A)
td(IDLE
COH)
WAKE INT
CLKOUT
A0
A15
WAKE INT can be any valid interrupt or RESET.
Figure 30. IDLE2 Entry and Exit Timing
LPM1
td(EX)
td(IDLE
COH)
td(IDLE
OSC)
á
á
RESET
CLKOUT
A0
A15
td(WAKE
OSC)
Figure 31. HALT Mode
LPM2
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