參數(shù)資料
型號： TMS320C542PGE-40
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 1/111頁
文件大?。?/td> 1467K
代理商： TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Data Bus With a Bus Holder Feature
D Address Bus With a Bus Holder Feature
(’548 and ’549 Only)
D Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space (’548 and ’549 Only)
D 192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
D On-Chip ROM with Some Configurable to
Program/Data Memory
D Dual-Access On-Chip RAM
D Single-Access On-Chip RAM (’548/’549)
D Single-Instruction Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for Better
Program and Data Management
D Instructions With a 32-Bit Long Word
Operand
D Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Full-Duplex Serial Port to Support 8- or
16-Bit Transfers (’541, ’LC545, and
’LC546 Only)
– Time-Division Multiplexed (TDM) Serial
Port (’542, ’543, ’548, and ’549 Only)
– Buffered Serial Port (BSP) (’542, ’543,
’LC545, ’LC546, ’548, and ’549 Only)
– 8-Bit Parallel Host-Port Interface (HPI)
(’542, ’LC545, ’548, and ’549)
– One 16-Bit Timer
– External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
D Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1 (JTAG) Boundary Scan
Logic
D 25-ns Single-Cycle Fixed-Point Instruction
Execution Time [40 MIPS] for 5-V Power
Supply (’C541 and ’C542 Only)
D 20-ns and 25-ns Single-Cycle Fixed-Point
Instruction Execution Time (50 MIPS and
40 MIPS) for 3.3-V Power Supply (’LC54x)
D 15-ns Single-Cycle Fixed-Point Instruction
Execution Time (66 MIPS) for 3.3-V Power
Supply (’LC54xA, ’548, ’LC549)
D 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply (’LC548, ’LC549)
D 10-ns and 8.3-ns Single-Cycle Fixed-Point
Instruction Execution Time (100 and 120
MIPS) for 3.3-V Power Supply (2.5-V Core)
(’VC549)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
1999, Texas Instruments Incorporated
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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