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參數(shù)資料
| 型號(hào)： | TMS320C40TABL40 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-Bit Digital Signal Processor |
| 中文描述： | 32位數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 49/132頁(yè) |
| 文件大小： | 1707K |
| 代理商： | TMS320C40TABL40 |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
general-purpose (GP) timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts:
underflow
,
overflow
,
timer compare
, and
period
interrupts
A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time
base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1
for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare
registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as
needed.
full-compare units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
values (from 0 to 16
μ
s) can be programmed into the compare register for the outputs of the three compare units.
The deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way of the
double-buffered ACTR register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with
programmable deadbands
, and two
independent PWMs by the GP-timer compares.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS320C40TABL50 | 32-Bit Digital Signal Processor |
| TMS320C40TABL60 | 32-Bit Digital Signal Processor |
| TMS320C44-50 | Digital Signal Processors |
| TMS320C44-60 | Digital Signal Processors |
| TMS320C44PDB-50 | DSP|32-BIT|CMOS|QFP|304PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320C40TABL50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Digital Signal Processor |
| TMS320C40TABL60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Digital Signal Processor |
| TMS320C44 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| TMS320C44-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Signal Processors |
| TMS320C44-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Signal Processors |
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